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19-1498; Rev 0; 6/99
KIT ATION EVALU BLE AVAILA
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
General Description
The MAX3890 serializer is ideal for converting 16-bitwide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers PECL serial data and clock outputs. A fully integrated PLL synthesizes an internal 2.5GHz serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference clock. A loopback data output is provided to facilitate system diagnostic testing. The MAX3890 is available in the extended temperature range (-40C to +85C) in a 64-pin TQFP exposedpaddle (EP) package. o Single +3.3V Supply o 495mW Power Consumption o Exceeds ANSI, ITU, and Bellcore Specifications o 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial Conversion o Clock Synthesis for 2.5Gbps o Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) o LVDS Parallel Clock and Data Inputs o Additional High-Speed Output for System Loopback Testing
Features
MAX3890
Applications
2.5Gbps SDH/SONET Transmission Systems 2.5Gbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross-Connects ATM Backplanes
PART
Ordering Information
TEMP. RANGE PIN-PACKAGE 64 TQFP-EP* MAX3890ECB -40C to +85C *EP = Exposed Paddle
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
155MHz REF. CLOCK INPUT
+3.3V
+3.3V TTL +3.3V 130 130 VCC 82 82 +3.3V
PDI0+ RCLK+ RCLK- CLKSET PDI0PDI15+ OVERHEAD GENERATION PDI15PCLKI+ PCLKIPCLKO+ PCLKOGND
VCC
SOS SDO+ SDO-
MAX3890
130 SCLKO+ SCLKOFIL+ FILSLBO+ SLBO82 82 130
MAX3867
330nF
OPTIONAL CONNECTION TO MAX3880 FOR SYSTEM LOOPBACK TESTING.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50).
________________________________________________________________ Maxim Integrated Products
1
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC .......................................................................-0.5V to +5V All Inputs, FIL+, FIL- ...............................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs (PCLKO)................................................10mA PECL Outputs (SDO, SCLKO)....................................50mA CML Outputs (SLBO)....................................................15mA Continuous Power Dissipation (TA = +85C) TQFP-EP (derate 44.8mW/C above +85C) ......................1W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential LVDS loads = 100 1%, PECL loads = 50 1% to (VCC - 2V), CML loads = 50 1% to VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current PECL OUTPUTS (SDO, SCLKO) TA = 0C to +85C TA = -40C TA = 0C to +85C Output Voltage Low VOL TA = -40C LVDS INPUTS AND OUTPUTS (PCLKO, PDI_, PCLKI, RCLKI) Input Voltage Range VI Differential input voltage = 100mV Differential Input Threshold VIDTH Threshold Hysteresis VHYST Differential Input Resistance RIN Output Voltage High VOH Output Voltage Low VOL |VOD| Differential Output Voltage Figure 5 Output Voltage High VOH Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of Single-Ended Output Resistance for Complementary Outputs |VOD| VOS VOS RO RO 40 95 2.5 1.125 VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC -1.83 0 -100 85 0.925 250 60 100 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.555 2.4 100 115 1.475 400 25 1.275 25 140 10 V V SYMBOL ICC CONDITIONS PECL outputs unterminated, SOS = low MIN TYP 150 MAX 230 UNITS mA
V mV mV V V mV mV V mV %
2
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, differential LVDS loads = 100 1%, PECL loads = 50 1% to (VCC - 2V), CML loads = 50 1% to VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER PROGRAMMING INPUT (CLKSET) CLKSET Input Current TTL INPUT (SOS) Input Voltage High Input Voltage Low Input Current High Input Current Low Differential Output Voltage Single-Ended Output Resistance VIH VIL IIH IIL |VOD| RO -10 -10 100 50 2.0 0.8 10 10 400 V V A A mV ICLKSET CLKSET = 0 or VCC 500 A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3890
CURRENT MODE LOGIC (CML) OUTPUTS (SLBO)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential LVDS load = 100 1%, PECL loads = 50 1% to (VCC - 2V), CML loads = 50 1% to VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER Serial Clock Rate Parallel Data Setup Time Parallel Data-Hold Time PCLKO to PCLKI Skew Output Jitter Generation (SCLKO) PECL Differential Output Rise/Fall Time Parallel Input Clock Rate Reference Clock Input (RCLKI) Rise/Fall Time Parallel Clock Output (PCLKO) Rise/Fall Time Serial Clock Output (SCLKO) to Serial-Data Output (SDO) Delay SYMBOL fSCLK tSU tH tSKEW 0 tR, tF fPCLKI tR, tF tR, tF tSCLK-SD 20% to 80%, f = 155.52MHz 20% to 80% SCLKO rising edge to SDO edge 110 CONDITIONS (Note 2) (Note 2) Figure 2 Jitter bandwidth = 12kHz to 20MHz, RCLK amplitude > |VIDTH| (Note 3) 20% to 80% 155.52 1.0 1.0 290 MIN 300 700 0 TYP 2.488 MAX UNITS GHz ps ps ns psRMS ps MHz ns ns ps
+4.0 3 120
Note 1: AC characteristics guaranteed by design and characterization. Note 2: Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel clock with rise/fall time = 1ns (20% to 80%). See Figure 2. Note 3: For fRCLK = 38.88MHz, the minimum reference clock amplitude is 200mV.
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
Typical Operating Characteristics
(VCC = +3.3V, PECL loads = 50 1%, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3890-01
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3890-02
200
180 SUPPLY CURRENT (mA)
160
140
120 PECL OUTPUTS UNTERMINATED 100 -50 -25 0 25 50 75 100 50ps/div TEMPERATURE (C)
SERIAL-DATA OUTPUT JITTER
fRCK = 155.52MHz
MAX3890-03
OUTPUT JITTER GENERATION vs. RCLK AMPLITUDE
MAX3890 toc04
3.0 OUTPUT JITTER GENERATION (ps) 2.5 2.0 1.5 1.0 0.5 0 fRCLK = 38.88MHz fRCLK = 51.84MHz
fRCK = 155.52MHz
fRCLK = 155.52MHz 100 150 200 250
fRCLK = 77.76MHz 300 350 400
5ps/div TOTAL WIDEBAND RMS JITTER = 2.155ps, PEAK-TO-PEAK JITTER = 15.7ps
RCLK AMPLITUDE (mV)
4
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
Pin Description
PIN 1, 17, 33, 48, 49, 63 2, 5, 7, 10, 13, 14, 32, 56, 60, 64 3 4 6 8 9 11 12 15 16 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 19, 21, 23, 25, 27, 29, 31, 35, 37, 39, 41, 43, 45, 47, 51, 53 54 55 57 58 NAME GND VCC SLBOSLBO+ SOS SCLKOSCLKO+ SDOSDO+ PCLKI+ PCLKIPDI15+ to PDI0+ Ground +3.3V Supply Voltage System Loopback Inverting Output. Enabled when SOS is high. System Loopback Noninverting Output. Enabled when SOS is high. System Loopback Output Select. System loopback disabled when low. Inverting PECL Serial Clock Output Noninverting PECL Serial Clock Output Inverting PECL Serial-Data Output Noninverting PECL Serial-Data Output Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. Inverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. Noninverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition. FUNCTION
MAX3890
PDI15- to PDI0PCLKO+ PCLKORCLK+ RCLK-
Inverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition. Noninverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. Inverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the RCLK inputs. Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the RCLK inputs. Reference Clock Rate Programming Pin: CLKSET = VCC: Reference Clock Rate = 155.52MHz CLKSET = Open: Reference Clock Rate = 77.76MHz CLKSET = 20k to GND: Reference Clock Rate = 51.84MHz CLKSET = GND: Reference Clock Rate = 38.88MHz Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-. Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
59
CLKSET
61 62
FILFIL+
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
_______________Detailed Description
The MAX3890 converts 16-bit-wide, 155Mbps data to 2.5Gbps serial data (Figure 1). It is composed of a 16bit parallel input register, a 16-bit shift register, control and timing logic, PECL output buffers, LVDS input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/frequency detector, loop filter/amplifier, voltage-controlled oscillator (VCO), and prescaler). The PLL synthesizes an internal 2.5Gbps reference used to clock the output shift register. This clock is generated by locking onto the external 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3890 on the rising transition of the parallel-clockinput signal (PCLKI). Proper operation is ensured if the parallel input register is latched within a window of time (t SKEW) that is defined with respect to the parallelclock-output signal (PCLKO). PCLKO is the synthesized 2.5Gbps internal serial-clock signal divided by 16. The allowable PCLKO-to-PCLKI skew is 0 to +4ns. This defines a timing window after the PCLKO rising edge, during which a PCLKI rising edge may occur (Figure 2).
System Loopback
The MAX3890 is designed to allow system loopback testing. The loopback outputs (SLBO+, SLBO-) of the MAX3890 may be directly connected to the loopback inputs of a deserializer (such as the MAX3880) for system diagnostics. To enable the SLBO outputs, apply a TTL logic-high signal to the SOS input. Note: The same signal that controls the SOS enable input may also be used to control the SIS enable input on the MAX3880.
PDI15+ PDI15LVDS
MAX3890
16-BIT PARALLEL INPUT REGISTER
PDI1+ PDI1LVDS
PDI0+ PDI0LVDS SOS CML LVDS PCLKIPRESCALER DIVIDE BY 16 LVDS SHIFT 16-BIT SHIFT REGISTER PECL SDO+ SDOSLBO+ SLBO-
PCLKI+
RCLKI+ LVDS RCLKIPLL
PHASE/FREQ DETECT
FILTER
VCO
LATCH
PECL
SCLKO+ SCLKO-
FIL+ FIL-CLKSET
PCLKO+ PCLKO-
Figure 1. Functional Diagram
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
PCLKO
tSKEW
PCLKI tSU PARALLEL INPUT DATA (PDI_) SERIAL OUTPUT DATA (SDO) *D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PDI 15 = D15; PDI14 = D14; ...PDI0 = D0. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA. VALID PARALLEL DATA* tH
Figure 2. Timing Diagram
Low-Voltage Differential-Signal Inputs and Outputs
The MAX3890 has LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mV to 400mV differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel clock LVDS outputs (PCLKO+, PCLKO-) require 100 differential DC termination between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PDI_+, PDI_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are
internally terminated with 100 differential input resistance, and therefore do not require external termination.
PECL Outputs
The serial-data PECL outputs (SDO+, SDO-, SCLKO+, SCLKO-) require 50 DC termination to (VCC - 2V) (see the Alternative PECL-Output Termination section).
Current-Mode Logic Outputs The system loopback outputs (SLBO+, SLBO-) of the MAX3890 are designed using CML. The configuration of the MAX3890 current-mode logic (CML) output circuit includes internal 50 back termination to V CC (Figure 3). These outputs are intended to drive a 50 transmission line terminated with a matched load impedance.
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
VCC VCC
50
50 SLBO+ 50 50
SLBOESD STRUCTURE SLBI+
SLBI-
GND OUTPUT CIRCUIT INPUT CIRCUIT
Figure 3. Current-Mode Logic
Applications Information
Alternative PECL-Output Termination
Figure 4 shows alternative PECL-output termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If ACcoupling is necessary, be sure that the coupling capacitor is placed following the 50 or Thevenin-equivalent DC termination.
+3.3V 130
130
MAX3890
SCLKO+ OR SDO+ Z0 = 50 PECL INPUTS
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3890 clock and data inputs and outputs.
SCLKOOR SDO-
Z0 = 50 82 82
MAX3890
SCLKO+ OR SDO+ Z0 = 50 HIGHIMPEDANCE INPUTS
SCLKOOR SDO-
Z0 = 50
50 VCC - 2V
50
Figure 4. Alternative PECL-Output Termination
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
PD+ D PDVPDSINGLE-ENDED OUTPUT VPD+ VOH RL = 100 V VOD
|VOD|
VOS VOL
VPD+ - VPDDIFFERENTIAL OUTPUT 0V (DIFF) 0V
+VOD VODp-p = VPD+ - VPD-VOD
Figure 5. Driver Output Levels
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
Pin Configuration
TOP VIEW
CLKSET RCLKPCLKO+ PCLKORCLK+ PDI0+ PDI1+ PDI0PDI1GND VCC GND
48 GND 47 PDI246 PDI2+ 45 PDI344 PDI3+ 43 PDI442 41
FIL+
VCC
FIL-
VCC
64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
GND VCC SLBOSLBO+ VCC SOS VCC SCLKOSCLKO+
1 2 3 4 5 6 7 8 9
PDI4+ PDI5PDI5+ PDI6+ PDI7PDI8PDI8+ GND
MAX3890
40
VCC 10 SDO- 11 SDO+ 12 VCC 13 VCC 14 PCLKI+ 15 PCLKI- 16
39 PDI638 37
36 PDI7+ 35 34 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PDI15-
PDI14-
PDI13-
PDI12-
PDI15+
PDI14+
PDI13+
PDI12+
PDI11+
PDI11-
PDI10+
PDI9+
PDI9-
GND
TQFP-EP
___________________Chip Information
TRANSISTOR COUNT: 4126
10
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PDI10-
VCC
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
Package Information
48L,TQFP.EPS 48L,TQFP.EPS
MAX3890
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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